In a conventional debug circuit of a signal processor, a command such as BRAKE is inserted to a program memory at a predetermined address where an inner circuit state is to be traced, so that the processor stops the program operation at an address just before the command of BRAKE, and then the processor supplies an external circuit with information of an internal circuit such as an arithmetic unit to bebug the program.
According to the conventional debug circuit of a signal processor, however, there is a disadvantage in that it is necessary to restart the program operation from the first address after finishing of the debug operation, as a result of conducting the command of BRAKE. Consequently, it is hard to carry out the debug operation at plural addresses of the program memory.